1. Field of the Invention
The invention relates to a semiconductor memory.
Semiconductor memories have memory cells to store an item of information in the form of a charge. A memory cell of a DRAM semiconductor memory has, by way of example, a trench capacitor and a selection transistor. A charge is stored in the trench capacitor in accordance with the information to be stored, the charge being transferred, through a driving of the selection transistor, through a word line to a bit line of the semiconductor memory. An evaluation circuit evaluates the voltage of the bit line so that the charge stored in the trench capacitor can be detected as information.
In order, as structures become ever smaller, to be able to realize a DRAM memory cell, for example, on the available space, concepts with a vertically disposed selection transistor are increasingly being investigated.
German Patent DE 199 54 867 C1, corresponding to U.S. Pat. No. 6,448,600 to Schloesser et al., discloses a DRAM cell configuration and a method for fabricating it in which a vertical selection transistor is provided. The known cell configuration has a trench capacitor that, in an upper end region, is connected to a horizontally disposed source-drain region. A lower source-drain region is formed in a manner offset with respect to the upper source-drain region and is connected to a vertical connecting channel. The connecting channel is led from the lower source-drain region upward to the bit line. A gate region constituting part of a word line is formed parallel to the connecting channel.
The known cell configuration has the disadvantage that a relatively large amount of area is required to form the memory cell.
It is accordingly an object of the invention to provide a semiconductor memory with vertical selection transistor that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that has a memory cell with a smaller area requirement.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a semiconductor memory, including at least one memory cell defining a trench having a lower part, the at least one memory cell having a trench capacitor formed in the lower part of the trench, the trench capacitor having a trench filling serving as a first electrode, a second electrode disposed outside the trench, and a dielectric layer electrically insulating the first electrode from the second electrode, a bit line disposed above the trench capacitor, and a vertically formed selection transistor having a perpendicular connecting channel forming therethrough an electrically conductive connection between the first electrode of the trench capacitor and the bit line, the connecting channel being formed laterally adjoining the trench, at least one word line associated with the at least one memory cell, the connecting channel being led upward in a direction of the bit line through the at least one word line, and a gate region of the selection transistor being formed laterally adjoining the connecting channel and above the trench filling as the first electrode. The vertically formed selection transistor can have a vertical connecting channel forming therethrough the electrically conductive connection between the first electrode of the trench capacitor and the bit line.
One advantage of the semiconductor memory according to the invention is that the connecting channel is formed in a manner laterally adjoining the trench filling of the trench capacitor, and that a gate region of the selection transistor is formed in a manner laterally adjoining the connecting channel and above the trench filling and the connecting channel constitutes an active region of the selection transistor. As such, less area is required to form the memory cell.
In accordance with another feature of the invention, the gate region surrounds the connecting channel. An improved activation of the active region of the connecting channel is made possible in this way. Moreover, a larger conduction channel that forms is achieved overall.
In accordance with a further feature of the invention, the gate region surrounds the connecting channel and is formed as part of the at least one word line.
In accordance with an added feature of the invention, the trench filling is covered by an insulation layer that is led with an over-area beyond a side edge of the trench filling. What is achieved in this way is that the trench filling, on the side of the over-area, is protected against the formation of a parasitic current. The formation of the over-area prevents the trench filling, on the side of the over-area, from forming a current to a connecting channel that adjoins the trench filling on the side. A crosstalk to an adjacent connecting channel that leads to an adjacent bit line is, thus, avoided.
In accordance with an additional feature of the invention, the trench has a side edge and an insulation layer covers the trench and has an over-area extending beyond the side edge of the trench.
A further reduction of the area required for forming the memory cell is achieved by virtue of the fact that at least one part of a second word line is disposed on the over-area above the trench filling. Consequently, the available area above the trench filling can be used for disposing both a first word line and a second word line. The first word line is used for driving the trench filling. The second word line is provided for driving an adjacent trench filling.
In accordance with yet another feature of the invention, there is provided a substantially vertical insulation layer isolating the second word line from the at least one word line and at least one part of the at least one word line and at least one part of the second word line being disposed above the trench. Preferably, a vertical insulation layer substantially isolates the first and second word lines. As a result, first, a simple fabrication method is made possible and, second, a large-area activation of the connecting channel by the word lines is achieved.
In accordance with yet a further feature of the invention, the at least one memory cell and the at least one word line are formed by lithography having a minimum resolution width and the insulation layer has a width less than the minimum resolution width.
In accordance with yet an added feature of the invention, the width of the insulation layer is less than the minimum resolution width F of the lithography used. This small width is achieved by virtue of the fact that, during the fabrication of the insulation layer, by way of example, a spacer technique is used to further reduce the minimum resolution.
In accordance with a concomitant feature of the invention, the at least one memory cell is a plurality of memory cells with a plurality of bit lines, the at least one word line is a plurality of word lines, the word lines are disposed substantially parallel to one another, the bit lines are disposed substantially parallel to one another, the word lines and the bit lines are substantially perpendicular to one another, the trench capacitors of the memory cells are disposed laterally offset with respect to one another from one of the bit lines to another of the bit lines, and the selection transistors of the memory cells for adjacent ones of the bit lines are disposed on opposite sides of a respective one of the trench capacitors.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor memory with vertical selection transistor, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.